Created for Arduino DUE & like boards, word size optimized for 12-bits data input.

FFT takes as input ANY size of array 8, 16, 32, 64, 128, 256, 512, 1024, 2048.

Max. size 2048 defined by LUT.

Library may run on different platform, only PROGMEM macros and variable declaration

type may need to be adjusted accordingly.

Algorithm tested on Arduino DUE and IDE 1.5.6-r2 (Tested on Linux OS only).

Timing results, in usec, fft-2048:

- Hamng – 864
- Revb – 817
- RDX4 – 6968
- GainR – 320
- Sqrt – 5297
- Sqrt2 – 405

There is two sub-functions for magnitude calculation, as you can see second one runs

more than 10x times faster, but it is less accurate, error in worst case scenario

may reach 5 %. Approximation based on

http://www.dspguru.com/dsp/tricks/magnitude-estimator

Short summary, DUE is ~15x times faster than UNO.

Analog Input – 0, Default sampling rate 48 000.

Link to file.

Don’t missed out, here UNO version of the RADIX4 library.

Enjoy!

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Edu

April 7, 2014 at 6:49 am

Hi,

We are testing the “UNO version of the RADIX4 library” and it is work perfectly as long as we use FFT windows size equal or smaller than 256. We are using Arduino Mega. Thanks for the hard work!!!.

E.

magiciant

April 9, 2014 at 8:22 pm

Answer to this issue is in the last paragraph of another blog.

http : // coolarduino.wordpress.com/2012/03/24/radix-4-fft-integer-math/

In short, there is an “optimization” in the code to make it run faster, and it works (as explained) for fft_size 128.

Actually, for fft_size = 256 you may just decrease ADC values by shifting right >> 1, and with fft_size = 512 , right >> 2. It’s simply means you downscale (downgrade) ADC to 9 or 8-bits. So multiple of fft gain G = 7 / 8 bit myltiply by 9 / 8-bit ADC values stay again in 16-bits range. If downgrading of the ADC data is not acceptable, than you should sacrifice a speed and turn off optimization, making this changes in the code:

FROM:

static inline void sum_dif_I(int a, int b, int &s, int &d) __attribute__((always_inline));

static inline void sum_dif_I(int a, int b, int &s, int &d)

{

s = (a+b);// >> 1; // Right Shift Limiter: OFF

d = (a-b);// >> 1; // Performance with RSL 25.5 millisec, w/o – 25.1 millisec.

}

TO:

static inline void sum_dif_I(int a, int b, int &s, int &d) __attribute__((always_inline));

static inline void sum_dif_I(int a, int b, int &s, int &d)

{

s = (a+b) >> 1; // Right Shift Limiter: OFF

d = (a-b) >> 1; // Performance with RSL 25.5 millisec, w/o – 25.1 millisec.

}

There is no problem in DUE library, as variables size equals to 32-bits, and with internal 12-bit ADC there is a room for 20-bits gain, or maximum fft_size can be 1048576 , and it’s well above 96 k memory of the chip.